Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication Overlapping Communications and Computations

Carmen N. Ojeda-Guerra, Roberto Esper-Chaín, M. Estupiñán, Elsa M. Macías, Álvaro Suárez. Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication Overlapping Communications and Computations. In Reiner W. Hartenstein, Andres Keevallik, editors, Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL 98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings. Volume 1482 of Lecture Notes in Computer Science, pages 396-400, Springer, 1998. [doi]

Abstract

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