COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization

Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. In International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy. pages 304-309, IEEE, 2010. [doi]

Abstract

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