Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks

Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross. Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst., 6(1):13-24, 2016. [doi]

@article{OnizawaJHG16,
  title = {Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks},
  author = {Naoya Onizawa and Hooman Jarollahi and Takahiro Hanyu and Warren J. Gross},
  year = {2016},
  doi = {10.1109/JETCAS.2016.2528721},
  url = {http://dx.doi.org/10.1109/JETCAS.2016.2528721},
  researchr = {https://researchr.org/publication/OnizawaJHG16},
  cites = {0},
  citedby = {0},
  journal = {IEEE J. Emerg. Sel. Topics Circuits Syst.},
  volume = {6},
  number = {1},
  pages = {13-24},
}