Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks

Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross. Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst., 6(1):13-24, 2016. [doi]

No reviews for this publication, yet.