A small die area and high linearity 10-bit capacitive three-level DAC - researchr publication authors

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Keigo Oshiro, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, Keiji Yoshida. A small die area and high linearity 10-bit capacitive three-level DAC. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012. pages 164-167, IEEE, 2012. [doi]

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