Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz Ergin. Reducing parity generation latency through input value aware circuits. In Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar, editors, Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009. pages 109-112, ACM, 2009. [doi]
Abstract is missing.