Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs

Jingzhao Ou, Viktor K. Prasanna. Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs. In Toomas P. Plaks, editor, Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. pages 55-61, CSREA Press, 2005.

@inproceedings{OuP05,
  title = {Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs},
  author = {Jingzhao Ou and Viktor K. Prasanna},
  year = {2005},
  tags = {design},
  researchr = {https://researchr.org/publication/OuP05},
  cites = {0},
  citedby = {0},
  pages = {55-61},
  booktitle = {Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2005, Las Vegas, Nevada, USA, June 27-30, 2005},
  editor = {Toomas P. Plaks},
  publisher = {CSREA Press},
  isbn = {1-932415-74-2},
}