Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu. A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. In 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. pages 56-57, IEEE, 2013. [doi]
Abstract is missing.