Girish Pahwa, Tapas Dutta, Amit Agarwal, Yogesh Singh Chauhan. Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach. In nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016. pages 49-54, IEEE, 2016. [doi]
@inproceedings{PahwaDAC16,
title = {Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach},
author = {Girish Pahwa and Tapas Dutta and Amit Agarwal and Yogesh Singh Chauhan},
year = {2016},
doi = {10.1109/ESSCIRC.2016.7598240},
url = {http://dx.doi.org/10.1109/ESSCIRC.2016.7598240},
researchr = {https://researchr.org/publication/PahwaDAC16},
cites = {0},
citedby = {0},
pages = {49-54},
booktitle = {nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
publisher = {IEEE},
isbn = {978-1-5090-2972-3},
}