ATPG for Delay Defects in Current Mode Threshold Logic Circuits

Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis. ATPG for Delay Defects in Current Mode Threshold Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 35(11):1903-1913, 2016. [doi]

Authors

Ashok Kumar Palaniswamy

This author has not been identified. Look up 'Ashok Kumar Palaniswamy' in Google

Spyros Tragoudas

This author has not been identified. Look up 'Spyros Tragoudas' in Google

Themistoklis Haniotakis

This author has not been identified. Look up 'Themistoklis Haniotakis' in Google