Ayan Palchaudhuri, Anindya Sundar Dhar. Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. In 24th IEEE International Conference on High Performance Computing, HiPC 2017, Jaipur, India, December 18-21, 2017. pages 104-113, IEEE, 2017. [doi]
Abstract is missing.