Ayan Palchaudhuri, Anindya Sundar Dhar. FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. In Michael B. Matthews, editor, 53rd Asilomar Conference on Signals, Systems, and Computers, ACSCC 2019, Pacific Grove, CA, USA, November 3-6, 2019. pages 1555-1559, IEEE, 2019. [doi]
Abstract is missing.