Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields

Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher. Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. on Circuits and Systems, 60-I(12):3195-3204, 2013. [doi]

Authors

Jeng-Shyang Pan

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Chiou-Yng Lee

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Pramod Kumar Meher

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