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Device- and system-level performance modeling for graphene P-N junction logic

Chenyun Pan, Azad Naeemi. Device- and system-level performance modeling for graphene P-N junction logic. In Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni, editors, Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012. pages 262-269, IEEE, 2012. [doi]

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Chenyun Pan

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Azad Naeemi

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