Chenyun Pan, Azad Naeemi. Device- and system-level performance modeling for graphene P-N junction logic. In Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni, editors, Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012. pages 262-269, IEEE, 2012. [doi]
@inproceedings{PanN12,
title = {Device- and system-level performance modeling for graphene P-N junction logic},
author = {Chenyun Pan and Azad Naeemi},
year = {2012},
doi = {10.1109/ISQED.2012.6187504},
url = {http://dx.doi.org/10.1109/ISQED.2012.6187504},
researchr = {https://researchr.org/publication/PanN12},
cites = {0},
citedby = {0},
pages = {262-269},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012},
editor = {Keith A. Bowman and Kamesh V. Gadepally and Pallab Chatterjee and Mark M. Budnik and Lalitha Immaneni},
publisher = {IEEE},
isbn = {978-1-4673-1034-5},
}