High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder

Amit Kumar Panda, Rakesh Palisetty, Kailash Chandra Ray. High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder. IEEE Trans. on Circuits and Systems, 67-I(11):3944-3953, 2020. [doi]

Abstract

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