An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits

Yu Pang, Katarzyna Radecka, Zeljko Zilic. An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. In Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011. pages 455-460, IEEE, 2011. [doi]

Authors

Yu Pang

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Katarzyna Radecka

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Zeljko Zilic

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