Goran Panic, Thomas Basmer, Klaus Tittelbach-Helmrich, Lukasz Lopacinski. Low power sensor node processor architecture. In 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010. pages 914-917, IEEE, 2010. [doi]
@inproceedings{PanicBTL10,
title = {Low power sensor node processor architecture},
author = {Goran Panic and Thomas Basmer and Klaus Tittelbach-Helmrich and Lukasz Lopacinski},
year = {2010},
doi = {10.1109/ICECS.2010.5724661},
url = {http://dx.doi.org/10.1109/ICECS.2010.5724661},
researchr = {https://researchr.org/publication/PanicBTL10},
cites = {0},
citedby = {0},
pages = {914-917},
booktitle = {17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010},
publisher = {IEEE},
isbn = {978-1-4244-8155-2},
}