Parth Parekh, Fei Yuan. Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator. In 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018, Montréal, QC, Canada, June 24-27, 2018. pages 191-194, IEEE, 2018. [doi]
Abstract is missing.