Parth Parekh, Fei Yuan 0005, Yushi Zhou. Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing. In 64th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021, Lansing, MI, USA, August 9-11, 2021. pages 1082-1085, IEEE, 2021. [doi]
Abstract is missing.