Marek Parfieniuk, Sang Yoon Park. On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. pages 391-396, IEEE, 2016. [doi]
@inproceedings{ParfieniukP16-0, title = {On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs}, author = {Marek Parfieniuk and Sang Yoon Park}, year = {2016}, doi = {10.1109/ISVLSI.2016.14}, url = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2016.14}, researchr = {https://researchr.org/publication/ParfieniukP16-0}, cites = {0}, citedby = {0}, pages = {391-396}, booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016}, publisher = {IEEE}, isbn = {978-1-4673-9039-2}, }