On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs

Marek Parfieniuk, Sang Yoon Park. On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. pages 391-396, IEEE, 2016. [doi]

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