Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors

Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy. Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. In Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim, editors, Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. pages 303-308, ACM, 2011. [doi]

@inproceedings{ParkKLKGR11,
  title = {Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors},
  author = {Sang Phill Park and Soo Youn Kim and Dongsoo Lee and Jae-Joon Kim and W. Paul Griffin and Kaushik Roy},
  year = {2011},
  url = {http://portal.acm.org/citation.cfm?id=2016871&CFID=34981777&CFTOKEN=25607807},
  researchr = {https://researchr.org/publication/ParkKLKGR11},
  cites = {0},
  citedby = {0},
  pages = {303-308},
  booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010},
  editor = {Vojin G. Oklobdzija and Barry Pangle and Naehyuck Chang and Naresh R. Shanbhag and Chris H. Kim},
  publisher = {ACM},
  isbn = {978-1-4503-0146-6},
}