Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1 - researchr publication authors

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Pilar Parra, Antonio J. Acosta, Manuel Valencia. Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. In Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido, editors, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Volume 2451 of Lecture Notes in Computer Science, pages 448-457, Springer, 2002. [doi]

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