A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-Processors - researchr publication authors

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Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D Souza, Amitava Majumdar. A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-Processors. In Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002. pages 726-735, IEEE Computer Society, 2002. [doi]

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