Correctly rounded floating-point division for DSP-enabled FPGAs

Bogdan Pasca. Correctly rounded floating-point division for DSP-enabled FPGAs. In Dirk Koch, Satnam Singh, Jim Tørresen, editors, 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012. pages 249-254, IEEE, 2012. [doi]

@inproceedings{Pasca12-0,
  title = {Correctly rounded floating-point division for DSP-enabled FPGAs},
  author = {Bogdan Pasca},
  year = {2012},
  doi = {10.1109/FPL.2012.6339189},
  url = {http://dx.doi.org/10.1109/FPL.2012.6339189},
  researchr = {https://researchr.org/publication/Pasca12-0},
  cites = {0},
  citedby = {0},
  pages = {249-254},
  booktitle = {22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012},
  editor = {Dirk Koch and Satnam Singh and Jim Tørresen},
  publisher = {IEEE},
  isbn = {978-1-4673-2257-7},
}