Vasilis F. Pavlidis, Eby G. Friedman. Interconnect delay minimization through interlayer via placement in 3-D ICs. In John Lach, Gang Qu, Yehea I. Ismail, editors, Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005. pages 20-25, ACM, 2005. [doi]
Abstract is missing.