A Power Model Combined of Architectural Level and Gate Level for Multicore Processors

Manman Peng, Yan Hu. A Power Model Combined of Architectural Level and Gate Level for Multicore Processors. In 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2013 / 11th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA-13 / 12th IEEE International Conference on Ubiquitous Computing and Communications, IUCC-2013, Melbourne, Australia, July 16-18, 2013. pages 1652-1655, IEEE, 2013. [doi]

@inproceedings{PengH13-0,
  title = {A Power Model Combined of Architectural Level and Gate Level for Multicore Processors},
  author = {Manman Peng and Yan Hu},
  year = {2013},
  doi = {10.1109/TrustCom.2013.204},
  url = {http://dx.doi.org/10.1109/TrustCom.2013.204},
  researchr = {https://researchr.org/publication/PengH13-0},
  cites = {0},
  citedby = {0},
  pages = {1652-1655},
  booktitle = {12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2013 / 11th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA-13 / 12th IEEE International Conference on Ubiquitous Computing and Communications, IUCC-2013, Melbourne, Australia, July 16-18, 2013},
  publisher = {IEEE},
}