A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS

Bei Peng, Guanzhong Huang, Hao Li 0001, Peiyuan Wan, Pingfen Lin. A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS. In Rakesh Patel, Tom Andre, Aurangzeb Khan, editors, 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011. pages 1-4, IEEE, 2011. [doi]

@inproceedings{PengHLWL11,
  title = {A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS},
  author = {Bei Peng and Guanzhong Huang and Hao Li 0001 and Peiyuan Wan and Pingfen Lin},
  year = {2011},
  doi = {10.1109/CICC.2011.6055421},
  url = {http://dx.doi.org/10.1109/CICC.2011.6055421},
  researchr = {https://researchr.org/publication/PengHLWL11},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011},
  editor = {Rakesh Patel and Tom Andre and Aurangzeb Khan},
  publisher = {IEEE},
  isbn = {978-1-4577-0222-8},
}