Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]

Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen. Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]. IEICE Electronic Express, 12(7):20158001, 2015. [doi]

@article{PengTLLJYC15a,
  title = {Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]},
  author = {Chunyu Peng and Youwu Tao and Wenjuan Lu and Zhengping Li and Xinchun Ji and Jinlong Yan and Junning Chen},
  year = {2015},
  url = {https://www.jstage.jst.go.jp/article/elex/12/7/12_12.20158001/_article},
  researchr = {https://researchr.org/publication/PengTLLJYC15a},
  cites = {0},
  citedby = {0},
  journal = {IEICE Electronic Express},
  volume = {12},
  number = {7},
  pages = {20158001},
}