CHOPPER: A Compiler Infrastructure for Programmable Bit-serial SIMD Processing Using Memory in DRAM

Xiangjun Peng, Yaohua Wang, Ming-Chang Yang. CHOPPER: A Compiler Infrastructure for Programmable Bit-serial SIMD Processing Using Memory in DRAM. In IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023, Montreal, QC, Canada, February 25 - March 1, 2023. pages 1275-1288, IEEE, 2023. [doi]

@inproceedings{PengWY23,
  title = {CHOPPER: A Compiler Infrastructure for Programmable Bit-serial SIMD Processing Using Memory in DRAM},
  author = {Xiangjun Peng and Yaohua Wang and Ming-Chang Yang},
  year = {2023},
  doi = {10.1109/HPCA56546.2023.10071070},
  url = {https://doi.org/10.1109/HPCA56546.2023.10071070},
  researchr = {https://researchr.org/publication/PengWY23},
  cites = {0},
  citedby = {0},
  pages = {1275-1288},
  booktitle = {IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023, Montreal, QC, Canada, February 25 - March 1, 2023},
  publisher = {IEEE},
  isbn = {978-1-6654-7652-2},
}