S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests

Ivan Perez 0004, Enrique Vallejo 0001, Ramón Beivide. S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests. IEEE Transactions on Computers, 70(6):819-832, 2021. [doi]

@article{PerezVB21,
  title = {S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests},
  author = {Ivan Perez 0004 and Enrique Vallejo 0001 and Ramón Beivide},
  year = {2021},
  doi = {10.1109/TC.2021.3068615},
  url = {https://doi.org/10.1109/TC.2021.3068615},
  researchr = {https://researchr.org/publication/PerezVB21},
  cites = {0},
  citedby = {0},
  journal = {IEEE Transactions on Computers},
  volume = {70},
  number = {6},
  pages = {819-832},
}