Steffen Peter, Tony Givargis. Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits. In Behavioral Synthesis for Hardware Security. pages 343-363, 2022. [doi]
@incollection{PeterG22,
title = {Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits},
author = {Steffen Peter and Tony Givargis},
year = {2022},
doi = {10.1007/978-3-030-78841-4_15},
url = {https://doi.org/10.1007/978-3-030-78841-4_15},
researchr = {https://researchr.org/publication/PeterG22},
cites = {0},
citedby = {0},
pages = {343-363},
booktitle = {Behavioral Synthesis for Hardware Security},
}