Tirex: A Target-Level Intermediate Representation for Compiler Exchange

Artur Pietrek, Florent Bouchez, Benoit Dupont De Dinechin. Tirex: A Target-Level Intermediate Representation for Compiler Exchange. In Florent Bouchez, Sebastian Hack, Eelco Visser, editors, Proceedings of the Workshop on Intermediate Representations. pages 13-20, 2011.


We introduce Tirex, a Textual Intermediate Representation for EXchanging target-level information between compiler optimizers and whole or parts of code generators (aka compiler back-end). The first motivation for this intermediate representation is to factor target-specific compiler optimizations into a single component, in case several compilers need to be maintained for a particular target (e.g., operating system compiler and application code compiler). Another motivation is to reduce the run-time cost of JIT compilation and of mixed mode execution, since the program to compile is already in a representation lowered to the level of the target processor.

We build Tirex by extending the existing Minimalist Intermediate Representation (MinIR), itself expressed as a YAML textual encoding of compiler structures. Besides the lowering at the target level, our extensions in Tirex include the program data stream and loop scoped information. Tirex is currently produced by the Open64 and the LLVM compilers, with a GCC producer under work. It is consumed by the LAO code generator, which has been used in several production compilers and an experimental CLI-JIT compiler.