Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448 - researchr publication references

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Michel Pignol, Thierry Parrain, Vincent Claverie, Christian BolÃ©at, Guy Estaves. Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448. In 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece. pages 182-184, IEEE, 2008. [doi]

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