Modeling and Mitigating Transient Errors in Logic Circuits

Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker. Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Sec. Comput., 8(4):537-547, 2011. [doi]

Abstract

Abstract is missing.