VERILAT: verification using logic augmentation and transformations

Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee. VERILAT: verification using logic augmentation and transformations. In ICCAD. pages 88-95, 1996. [doi]

Authors

Dhiraj K. Pradhan

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Debjyoti Paul

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Mitrajit Chatterjee

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