Priyank H. Prajapati, Anand D. Darji. FPGA Implementation of MRMN with Step-Size Scaler Adaptive Filter for Impulsive Noise Reduction. CSSP, 39(7):3682-3710, 2020. [doi]
@article{PrajapatiD20,
title = {FPGA Implementation of MRMN with Step-Size Scaler Adaptive Filter for Impulsive Noise Reduction},
author = {Priyank H. Prajapati and Anand D. Darji},
year = {2020},
doi = {10.1007/s00034-019-01339-z},
url = {https://doi.org/10.1007/s00034-019-01339-z},
researchr = {https://researchr.org/publication/PrajapatiD20},
cites = {0},
citedby = {0},
journal = {CSSP},
volume = {39},
number = {7},
pages = {3682-3710},
}