P. W. Chandana Prasad, Bruce Mills, Ali Assi, S. M. N. Arosha Senanayake, V. C. Prasad. Evaluation time Estimation for Pass Transistor Logic circuits. In Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia. pages 422-428, IEEE Computer Society, 2006. [doi]
Abstract is missing.