Analysis of a Fully-Scalable Digital Fractional Clock Divider

Thomas B. Preuber, Rainer G. Spallek. Analysis of a Fully-Scalable Digital Fractional Clock Divider. In 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA. pages 173-177, IEEE Computer Society, 2006. [doi]

@inproceedings{PreuberS06,
  title = {Analysis of a Fully-Scalable Digital Fractional Clock Divider},
  author = {Thomas B. Preuber and Rainer G. Spallek},
  year = {2006},
  doi = {10.1109/ASAP.2006.14},
  url = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.14},
  tags = {analysis},
  researchr = {https://researchr.org/publication/PreuberS06},
  cites = {0},
  citedby = {0},
  pages = {173-177},
  booktitle = {2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2682-9},
}