Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár. Fast just-in-time translated simulator for ASIP design. In Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus, editors, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011. pages 279-282, IEEE, 2011. [doi]
Abstract is missing.