Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha. V::t:: balancing and device sizing towards high yield of sub-threshold static logic gates. In Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan, editors, Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007. pages 355-358, ACM, 2007. [doi]
@inproceedings{PuGCH07,
title = {V::t:: balancing and device sizing towards high yield of sub-threshold static logic gates},
author = {Yu Pu and Jose de Jesus Pineda de Gyvez and Henk Corporaal and Yajun Ha},
year = {2007},
doi = {10.1145/1283780.1283857},
url = {http://doi.acm.org/10.1145/1283780.1283857},
tags = {logic},
researchr = {https://researchr.org/publication/PuGCH07},
cites = {0},
citedby = {0},
pages = {355-358},
booktitle = {Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007},
editor = {Diana Marculescu and Anand Raghunathan and Ali Keshavarzi and Vijaykrishnan Narayanan},
publisher = {ACM},
isbn = {978-1-59593-709-4},
}