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Optimized hardware algorithm for integer cube root calculation and its efficient architecture

Rachmad Vidya Wicaksana Putra, Trio Adiono. Optimized hardware algorithm for integer cube root calculation and its efficient architecture. In 2015 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2015, Nusa Dua Bali, Indonesia, November 9-12, 2015. pages 263-267, IEEE, 2015. [doi]

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Rachmad Vidya Wicaksana Putra

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Trio Adiono

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