Detection of gate-oxide defects with timing tests at reduced power supply

Xi Qian, Chao Han, Adit D. Singh. Detection of gate-oxide defects with timing tests at reduced power supply. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012. pages 120-126, IEEE, 2012. [doi]

@inproceedings{QianHS12,
  title = {Detection of gate-oxide defects with timing tests at reduced power supply},
  author = {Xi Qian and Chao Han and Adit D. Singh},
  year = {2012},
  doi = {10.1109/VTS.2012.6231090},
  url = {http://dx.doi.org/10.1109/VTS.2012.6231090},
  researchr = {https://researchr.org/publication/QianHS12},
  cites = {0},
  citedby = {0},
  pages = {120-126},
  booktitle = {30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012},
  publisher = {IEEE},
  isbn = {978-1-4673-1074-1},
}