Keni Qiu, Weigong Zhang, Xiaoqiang Wu, Xiaoyan Zhu, Jing Wang, Yuanchao Xu, Chun Jason Xue. Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors. In Sascha Ossowski, editor, Proceedings of the 31st Annual ACM Symposium on Applied Computing, Pisa, Italy, April 4-8, 2016. pages 1710-1716, ACM, 2016. [doi]
@inproceedings{QiuZWZWXX16,
title = {Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors},
author = {Keni Qiu and Weigong Zhang and Xiaoqiang Wu and Xiaoyan Zhu and Jing Wang and Yuanchao Xu and Chun Jason Xue},
year = {2016},
doi = {10.1145/2851613.2851670},
url = {http://doi.acm.org/10.1145/2851613.2851670},
researchr = {https://researchr.org/publication/QiuZWZWXX16},
cites = {0},
citedby = {0},
pages = {1710-1716},
booktitle = {Proceedings of the 31st Annual ACM Symposium on Applied Computing, Pisa, Italy, April 4-8, 2016},
editor = {Sascha Ossowski},
publisher = {ACM},
isbn = {978-1-4503-3739-7},
}