Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Keni Qiu, Weigong Zhang, Xiaoqiang Wu, Xiaoyan Zhu, Jing Wang, Yuanchao Xu, Chun Jason Xue. Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors. In Sascha Ossowski, editor, Proceedings of the 31st Annual ACM Symposium on Applied Computing, Pisa, Italy, April 4-8, 2016. pages 1710-1716, ACM, 2016. [doi]

The following publications are possibly variants of this publication:

BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processorsKeni Qiu, Yujie Zhu, Yuanchao Xu, Qirun Huo, Chun Jason Xue. mj, 83:137-146, 2019. [doi]

Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded SystemsKeni Qiu, Mengying Zhao, Qing'an Li, Chenchen Fu, Chun Jason Xue. tcad, 33(3):329-342, 2014. [doi]

Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systemsKeni Qiu, Mengying Zhao, Chenchen Fu, Liang Shi, Chun Jason Xue. asap 2013: 83-86 [doi]

A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT DevicesMimi Xie, Chen Pan, Youtao Zhang, Jingtong Hu, Yongpan Liu, Chun Jason Xue. micro, 39(1):24-32, 2019. [doi]

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPsAdwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das. dac 2012: 243-252 [doi]

runs on WebDSL