High-Performance Pipelined Architecture for Tree-Based IP Lookup Engine on FPGA

Yun Qu, Viktor K. Prasanna. High-Performance Pipelined Architecture for Tree-Based IP Lookup Engine on FPGA. In 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, Cambridge, MA, USA, May 20-24, 2013. pages 114-123, IEEE, 2013. [doi]

@inproceedings{QuP13-0,
  title = {High-Performance Pipelined Architecture for Tree-Based IP Lookup Engine on FPGA},
  author = {Yun Qu and Viktor K. Prasanna},
  year = {2013},
  doi = {10.1109/IPDPSW.2013.168},
  url = {http://doi.ieeecomputersociety.org/10.1109/IPDPSW.2013.168},
  researchr = {https://researchr.org/publication/QuP13-0},
  cites = {0},
  citedby = {0},
  pages = {114-123},
  booktitle = {2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, Cambridge, MA, USA, May 20-24, 2013},
  publisher = {IEEE},
}