High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

Yun R. Qu, Viktor K. Prasanna. High-Performance and Dynamically Updatable Packet Classification Engine on FPGA. IEEE Trans. Parallel Distrib. Syst., 27(1):197-209, 2016. [doi]

@article{QuP16,
  title = {High-Performance and Dynamically Updatable Packet Classification Engine on FPGA},
  author = {Yun R. Qu and Viktor K. Prasanna},
  year = {2016},
  doi = {10.1109/TPDS.2015.2389239},
  url = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2015.2389239},
  researchr = {https://researchr.org/publication/QuP16},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. Parallel Distrib. Syst.},
  volume = {27},
  number = {1},
  pages = {197-209},
}