A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits - researchr publication

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Kaamran Raahemifar, Majid Ahmadi. A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits. In 8th Great Lakes Symposium on VLSI (GLS-VLSI 98), 19-21 February 1998, Lafayette, LA, USA. pages 249, IEEE Computer Society, 1998. [doi]

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