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Scalable instruction set simulator for thousand-core architectures running on GPGPUs

Shivani Raghav, Martino Ruggiero, David Atienza, Christian Pinto, Andrea Marongiu, Luca Benini. Scalable instruction set simulator for thousand-core architectures running on GPGPUs. In Waleed W. Smari, John P. McIntire, editors, Proceedings of the 2010 International Conference on High Performance Computing & Simulation, HPCS 2010, June 28 - July 2, 2010, Caen, France. pages 459-466, IEEE, 2010. [doi]

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Shivani Raghav

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Martino Ruggiero

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David Atienza

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Christian Pinto

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Andrea Marongiu

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Luca Benini

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